An exemplary embodiment relates generally to a method of manufacturing semiconductor devices and, more particularly, to a method of manufacturing semiconductor devices in which a gap-fill process can be easily performed.
A semiconductor device typically includes a number of gates and metal lines.
To form the gates or metal lines, a gap-fill process of filling contact holes or trenches with a material to be formed within the contact holes or trenches may be used. Meanwhile, with an increase in the degree of integration of semiconductor devices, the intervals between the gates and between the metal lines and the width thereof are narrowed. Accordingly, a void or seam is generated within the contact hole or the trench, making it gradually more difficult to perform the gap-fill process.
FIG. 1 is a cross-sectional view illustrating some problems of known semiconductor devices.
To describe the gap-fill process from among processes of manufacturing semiconductor devices, a section of a part of a semiconductor device is shown as an example.
A first dielectric interlayer 12 and contact plugs 14 are formed over a semiconductor substrate 10 having junctions 10a formed therein. Etch-stop patterns 16 and second interlayer insulating patterns 18 are formed over the first dielectric interlayer 12, and trenches T1 are formed over the contact plugs 14. A barrier layer 20 and a seed layer 22 are sequentially formed on a surface of the second interlayer insulating patterns 18, the etch-stop patterns 16, and the contact plugs 14, including the trenches T1. The barrier layer 20 and the seed layer 22 are typically formed by a physical vapor deposition (PVD) method. In the case where a top width and a bottom width of the trench T1 are similar (or identical) in size, when a process of forming the barrier layer 20 and the seed layer 22 is performed, overhangs OH1 may be generated in upper parts of the second interlayer insulating patterns 18 having the trenches T1 formed therein. If the overhangs OH1 are generated, the barrier layer 20 and the seed layer 22 become thicker in an upper part of the trench T1 than in a lower part of the trench T1. Accordingly, a top width of the trench T1 becomes narrower than a bottom width of the trench T1. If a metal layer 24 for metal lines is formed in the state in which the overhangs OH1 formed, a void A1 may be generated within the trench T1. In other words, if the overhangs OH1 re generated, a top width of the trenches T1 is narrowed. Consequently, the upper part of the trenches T1 may be fully covered with the metal layer 24 before the lower part of the trench T1 is filled with the metal layer 24, thereby generating voids A1.
If a subsequent etch process is performed in the state in which the voids A1 are generated, the voids A1 may be exposed. An etchant or an etch gas can infiltrate into the exposed portions, and etch damage can be generated within the metal layer 24. Such etch damage may cause an increase in the resistance of metal lines. In particular, since the etch damage may deteriorate the electrical properties of semiconductor devices, reliability of the semiconductor devices may deteriorate.